The present invention relates to a liquid crystal display apparatus and a data driver having a sampling pulse generating circuit that generates a plurality of sampling pulses for carrying out the sampling of an inputted signal in accordance with an inputted clock signal.
FIG. 5 shows an example of a conventional driver monolithic-type liquid crystal display apparatus. As shown in FIG. 5, there are provided, on a transparent substrate such as a glass substrate and a quartz substrate, a data driver 101, a gate driver 102, and a display section 103, thereby constituting a driver monolithic-type liquid crystal display apparatus.
To the data driver 101, are inputted a start pulse sp (control signal), clock signals ck and ckb, and video signals 1 and 2 (image signals), respectively.
To the gate driver 102, are inputted signals such as a start pulse spg and clock signals ckg and ckgb. The display section 103 is constituted by thin film transistors (TFT) 104 in a matrix manner. The gate terminals of the respective thin film transistors 104, constituting the display section 103, are connected to gate bus lines G1, G2, . . . , Gn that are extended from the respective outputs of the gate driver 102. The source terminals of the respective thin film transistors 104 are connected to source bus lines {circle around (1)}, {circle around (2)}, . . . , n that are extended from the respective outputs of the data driver 101. The drain terminals of the respective thin film transistors 104 are connected to pixel capacitors 105 (pixel capacity) formed by transparent electrodes and opposite electrodes.
As shown in FIG. 6, the data driver 101 is constituted by a sampling pulse generating circuit 201 and analog switches 202 for sampling the image signals (the video signals 1 and 2 (inputted signals)) that were inputted into the data driver 101.
The sampling pulse generating circuit 201, as shown in FIG. 7(a), is constituted by (1) a shift register having a plurality of D-type flip-flops 301 that are cascade connected with each other and (2) AND circuits 302 for carrying out the operation of logical product with respect to the respective adjoining D-type flip-flops 301. The adjoining outputs (adjoining two outputs among the outputs Q1 through Q5 in FIG. 7(a)) of the respective stages of the shift register are inputted into the corresponding AND circuit 302.
The following explanation deals with the operation of the conventional liquid crystal display apparatus. Upon receipt of the start pulse sp, and the clock signals ck and ckb, the sampling pulse generating circuit 201, as shown in a timing chart of FIG. 7(b), consecutively outputs the first stage output SAM1, the second stage output SAM2, the third stage output SAM3, . . . , respectively, these outputs being sampling pulses.
To the sampling pulse generating circuit 201, at the timing shown in FIG. 8, are inputted the video signals 1 and 2 (image signals) that are the image signals obtained by being subject to time base extension in which the original image signals are twice time-base-extended. In accordance with the first stage output SAM1, the second stage output SAM2, the third stage output SAM3, . . . , the display image data are written into the source bus line capacitor through a sample hold circuit composed of the analog witches 202 and hold capacitor (capacity) formed by the source bus lines {circle around (1)}, {circle around (2)}, . . . , n that constitute the display section 103.
While writing the display image data into the respective source bus lines {circle around (1)}, {circle around (2)}, . . . , n in accordance with the sampling pulses, i.e., the first stage output SAM1, the second stage output SAM2, the third stage output SAM3, . . . , the gate bus line Gn (the output of the gate driver) is active, thereby the data, written into the respective source bus lines {circle around (1)}, {circle around (2)}, . . . , n through the thin film transistors 104 that are connected to the gate bus line Gn, are consecutively stored into the pixel capacitors 105 constituting the display section 103. Then, the sampling is finished with respect to the image data that correspond to the amount of one horizontal period. After having finished the writing of the data into the pixel capacitors 105, the gate bus line Gn becomes non-active. Until the display image data that correspond to the amount of the next frame period, the image data, written into the pixel capacitors 105, is maintained, thereby carrying out the image display of the liquid crystal display apparatus.
When carrying out the sampling of the image data in accordance with the foregoing operations, the actual sampling pulses outputted from the sampling pulse generating circuit 201 (for example, in the case of FIG. 6, the sampling pulses correspond to the first stage output SAM1, the second stage output SAM2, the third stage output SAM3, and the fourth stage output SAM4) have blunt wave forms, as shown in FIG. 9, due to additional capacity such as gate capacity of the analog switch 202 to be driven. When the sampling pulse becomes blunt, there occurs time Tob during which the n-th stage output SAMn overlaps with the (n+1)-th stage output SAMn+1.
In the case where the sampling of the image data is carried out, the data at the time when the sampling pulse turns off is written into the hold capacitor (in the case of the liquid crystal display apparatus, the hold capacitor correspond to the capacitor formed by the source bus lines). At this time, prior to the time Tob just before the n-th stage output SAMn perfectly turns off, the (n+1)-th stage output SAMn+1 turns on, thereby causing a noise in the image data to occur due to the charging and discharging of the source bus line capacitor. This results in that the appropriate sampling of the image data can not be carried out.
In order to overcome the foregoing problem, the following arrangement is proposed (see FIG. 10). As shown in FIG. 10, the logical product operation is carried out by an AND circuit 603 with respect to each stage output of the sampling pulse generating circuit 201 and a signal that is obtained by delaying the above-mentioned each stage output so as to narrow the pulse width of each stage output. More specifically, the n-th stage AND circuit 603 carries out the logical product operation with respect to the n-th stage output SAMn and a signal outputted from the n-th stage delay circuit 602 delaying the n-th stage output SAMn so as to narrow the pulse width of the n-th stage output SAMn.
With the foregoing arrangement, as shown in FIG. 11 after the n-th stage AND circuit 603 carries out the logical product operation with respect to the n-th stage output SAMn and the delayed signal SAMdn outputted from the n-th stage delay circuit 602, the resultant signal SAMnxe2x80x2 thus subject to the logical product operation is outputted as the n-th stage output from the sampling pulse generating circuit 201. Similarly, after the (n+1)-th stage AND circuit 603 carries out the logical product operation with respect to the (n+1)-th stage output SAMn+1 and the delayed signal SAMdn+1xe2x80x2 outputted from the (n+1)-th stage delay circuit 602, the resultant signal SAMn+1xe2x80x2 thus subject to the logical product operation is outputted as the (n+1)-th stage output from the sampling pulse generating circuit 201.
Since the time duration (Td1 through Td4 in FIG. 11) is provided for each stage output (sampling pulse), it is avoidable that the adjoining outputs SAMnxe2x80x2 and SAMn+1xe2x80x2 overlap with each other, thereby reducing the noise occurred in the image data.
As shown in FIG. 12, another conventional arrangement is proposed so as to narrow the pulse width of the sampling pulse (see the timing chart of FIG. 13), in which a delay circuit 803 for delaying the clock signal ck, a delay circuit 802 for delaying the clock signal ckb, and an AND circuit 804 for carrying out the logical product operation with respect to each stage output from the sampling pulse generating circuit 201 and either one of the output of the delay circuit 802 or 803.
Here, with reference to the timing chart shown in FIG. 11, the following explanation deals with more specific operations as to how to narrow the pulse width of the sampling pulse of the data driver having an arrangement shown in FIG. 10.
The n-th delay circuit 602 delays, by the delaying amount of Tdn, the n-th stage output SAMn of the sampling pulse generating circuit 201. Thus, the pulse width of the sampling pulse is narrowed by the delaying amount of Tdn. Accordingly, it is not preferable to set too much the delaying amount of Tdn. Because of this, it is likely that the adjoining outputs SAMnxe2x80x2 and SAMn+1xe2x80x2 overlap with each other when the delaying amount Td1, Td2, . . . of each delay circuit 602 is not uniform due to the fact that the characteristics of the thin film transistors constituting each delay circuit 602 are not uniform or other fact. This results in that it becomes impossible to carry out the sampling of the image data with accurate timing without being affected by some noises.
Furthermore, when controlling the sampling pulse width with the delay circuit 602 for each stage of the sampling pulse generating circuit 201, it is necessary to prepare the delay circuits 602 and AND circuits 603, such that the number of these circuits 602 and 603 is the same as the number of the required sampling pulses. As a result the packaging (mounting) area for the sampling pulse generating circuit 201 becomes increased.
According to the arrangement of the data driver shown in FIG. 12, the delay circuits 802 and 803, instead of the delay circuit 602, are provided in the inputting section of the data driver. Unlike the case of FIG. 10, this ensures that the sampling timing becomes uniform even though the characteristics of the respective delay circuits 602 are not uniform.
However, the load to be driven by the output of the delay circuit 802 is equal to the sum of the input load capacity of the (2k+1)-th (k=0, 1, 2, - . . . ) stage AND circuit 804. Similarly, the load to be driven by the output of the delay circuit 803 is equal to the sum of the input load capacity of the 2k-th (k=0, 1, 2, - - - ) stage AND circuits 804. This causes the problem that the delay circuits 802 and 803 must drive a heavy load, respectively.
Moreover, in the case of the arrangement shown in FIG. 12, unlike the case of the arrangement shown in FIG. 10, it is not necessary to provide the delay circuits 602 for each stage of the sampling pulse generating circuit 201. However, it is necessary to provide the AND circuits 804 whose number is identical with the required sampling pulses, thereby causing the packaging area to become large for realizing the data driver.
Note that Japanese unexamined patent publication No. 5-297834 (Publication Date: Nov. 12, 1993), Japanese unexamined patent publication No. 6-105263 (Publication Date: Apr. 15, 1994), and Japanese unexamined patent publication No. 11-175019 (Publication Date: Jul. 2, 1999) disclose the following technique. More specifically, by considering a delay of image signal due to the distributed constant of transmission lines for video signals and adjusting the phase of shift clock for driving the data driver in accordance with such a delay, the sampling timing of the image signal is adjusted so as to be coincident with the adequate point of the image data, thereby ensuring the sampling of image data with accuracy, which is the object of the techniques disclosed in the foregoing Japanese unexamined patent publications.
It is an object of the present invention to avoid active periods of respective adjoining sampling pulses overlapping with each other so as to reduce an error that occurs in image data during sampling, which is different from the foregoing publications.
In order to achieve the foregoing object, a liquid crystal display apparatus in accordance with the present invention having a sampling pulse generating circuit for generating a plurality of sampling pulses that carry out sampling of inputted signal, in which the inputted signal is sampled in accordance with the sampling pulse so as to be written into a display section as a display data is characterized by having the following arrangement.
More specifically, in the liquid crystal display apparatus, the sampling pulse generating circuit generates the sampling pulses in accordance with a clock signal whose duty ratio of a high level period with respect to a low level period is less than 50 percent.
With the arrangement of the liquid crystal display apparatus, the sampling pulse is generated by the sampling pulse generating circuit and inputted signal to be displayed in accordance with the sampling pulse is sampled, and the sampling result is written into the display section as the display data so that the display section displays the inputted signal.
The wave form of the sampling pulse is blunt due to such as the additional capacity formed by such as devices (elements) to be driven and wirings through which the sampling pulse is transmitted. This causes the following problem. More specifically, in the case where the duty ratio of the sampling pulse to be generated is fixed to 50 percent, there occurs the period in which the adjoining sampling pulses overlap with each other in the vicinity of the edges (the rising-up edges and falling-down edges). As a result, the sampling of the inputted signal can not be carried out with accuracy, and the sampling result contains an error, thereby causing that the accurate display data is not written into the display section.
In order to overcome the problem, a variety of proposals have been proposed in which the pulse width of the sampling pulse that has been generated is narrowed. However, in such proposals, the number of the circuit elements require such as a delay circuit and an AND circuit for controlling the pulse width of the sampling pulse, is as many as the number of the sampling pulses. This causes the packaging (mounting) area of the sampling pulse generating circuit to increase. Further, in the case where the delay circuit is provided, the delay circuit is required to have the driving ability in accordance with the number of the sampling pulses.
As the conventional arts other than the foregoing ones, it is known that a delay due to the distributed constant of transmission lines for the inputted signal is considered and the phase of shift clock for driving the data driver is adjusted in accordance with such a delay so as to avoid the foregoing overlapping. Such a case, however, causes changes the circuit arrangement and operation control to become very complicated.
In contrast, according to the liquid crystal display apparatus of the present invention, the sampling pulse is generated in accordance with the clock signal whose duty ratio of a high level period with respect to a low level period is less than 50 percent. More specifically, when the duty ratio of a high level period with respect to a low level period of the clock signal is less than 50 percent, it is avoidable that the adjoining sampling pulses which are generated by the sampling pulse generating circuit overlap with each other. Since this allows the sampling of the inputted signal is carried out with accuracy, it is avoided that the sampling result has an error, thereby allowing the accurate display data to be written into the display section. Accordingly, without making the circuit arrangement and operation control complicated, and without considering the driving ability of the delay circuit, a liquid crystal display apparatus with extremely high display reliability can be realized.
In order to achieve the foregoing object, a data driver in accordance with the present invention having a sampling pulse generating circuit for generating a plurality of sampling pulses that carry out sampling of inputted signal, in which the inputted signal is sampled in accordance with the sampling pulse so as to be outputted as a display data is characterized by having the following arrangement.
More specifically, in the data driver, the sampling pulse generating circuit generates the sampling pulse in accordance with a clock signal whose duty ratio of a high level period with respect to a low level period is less than 50 percent.
With this arrangement of the data driver, the sampling pulse is generated by the sampling pulse generating circuit, an inputted signal to be displayed in accordance with the sampling pulse is sampled, and the sampling result is written into the display section as the display data.
The wave form of the sampling pulse is blunt due to such as the additional capacity formed by such as devices (elements) to be driven and wirings through which the sampling pulse is transmitted. This causes the following problem. More specifically, in the case where the duty ratio of the sampling pulse to be generated is fixed to 50 percent, there occurs the period in which the adjoining sampling pulses overlap with each other in the vicinity of the edges. As a result, the sampling of the inputted signal can not be carried out with accuracy, and the sampling result contains an error, thereby causing accurate display data not to be written into the display section.
In order to overcome the problem, a variety of proposals have been proposed in which the pulse width of the sampling pulse that has been generated is narrowed. However, in such proposals, the number of the circuit elements required, such as a delay circuit and an AND circuit for controlling the pulse width of the sampling pulse, is as many as the number of the sampling pulses. This causes the mounting area of the sampling pulse generating circuit to increase. Further, in the case where the delay circuit is provided, the delay circuit is required to have the driving ability in accordance with the number of the sampling pulses.
As the conventional arts other than the foregoing ones, it is known that a delay due to the distributed constant of transmission lines for the inputted signal is considered and the phase of shift clock for driving the data driver is adjusted in accordance with such a delay so as to avoid the foregoing overlapping. Such a case, however, causes the circuit arrangement and operation control to become very complicated.
In contrast, according to the data driver of the present invention, the sampling pulse is generated in accordance with the clock signal whose duty ratio of a high level period with respect to a low level period is less than 50 percent.
More specifically, when the duty ratio of the clock signal of a high level period with respect to a low level period is less than 50 percent, it is avoidable that the adjoining sampling pulses which are generated by the sampling pulse generating circuit overlap with each other. Since this allows the sampling of the inputted signal to be carried out with accuracy, it is avoided that the sampling result has an error, thereby allowing accurate display data to be written into the display section. Accordingly, without making the circuit arrangement and operation control complicated, and without considering the driving ability of the delay circuit, it a liquid crystal display apparatus with extremely high display reliability can be realized.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitative of the present invention.